25.7.6 Interrupts

Each channel has the ability to generate an interrupt base on the following events:

• Channel detected a start trigger,CHINTFk.SD. Set on the detection of the start trigger which was configured by CHCTRLBk.TRIG and CHCTRLAk.ENABLE=1.
• Channel transfer aborted due to an abort trigger CHINTFk.TA
• Current cell transfer completed (CHINTFk.CC). Asserts each time a cell transfer completes. Also set at the end of the block transfer.
• Block transfer completed (CHINTFk.BC). Asserts at the completion of a block transfer, or when a block transfer aborts due to an abort trigger.
• Block transfer half completed (CHINTFk.BH). Asserts when the channel has written out more than half of the block based on the Block Transfer Size.
• Linked list complete (CHINTFk.LL). Asserts when the DMA encounters a NULL pointer value in register CHNXTk.NXT when attempting to load a descriptor.
• Read bus error encountered (CHINTFk.RDE). Asserts when the system bus matrix issues a client error response to a read request.
• Write bus error encountered (CHINTFk.WRE). Asserts when the system bus matrix issues a client error response to a write request.

The channel interrupts are logically OR’ed together by channel priority to generate 4 interrupts.