25.7.3 Block Transfer
Each DMA channel performs data transfers on a trigger event. A trigger event is either a hardware signal from the device event system, a hardware signal from a peripheral, or a write to the CHCTRLAk.SWFRC register field. The smallest amount of data transferred on a trigger event is defined as a cell transfer. A block transfer may consist of multiple cell transfers as show in the following figure. The DMA provides flexibility in defining the cell transfer size and block transfer size. However, the block transfer size is always greater than or equal to the cell transfer size. A block transfer size does not have to be an integer multiple of the cell transfer size.
To specify a block transfer, a DMA channel minimally requires the following
- Source Start Address
- Destination Start Address
- Block Transfer Size
- Cell Transfer Size
- Source Cell Stride Size
- Destination Cell Stride Size
- Read Address Sequence Mode
- Write Address Sequence Mode
- Start trigger event source
Once configured a channel will wait for the trigger event to initiate a transfer. On the trigger event, the channel requests access to DMAR. The DMA FSM arbitrates access based on channel and user selected priorities. See Channel Priorities for details on how arbitration takes place.
The channel issues read requests of the source data, either in burst fashion or as single transactions until the channel FIFO is full or is not capable of accepting another burst. The DMA makes the determination of using a burst transfer or single requests based on the Read Address Sequence Mode setting and address alignment of the source data. The channel request another read transaction when the channel FIFO has enough room to accept data. The read process continues until the number of bytes read equals the Cell Transfer Size.
On the write size of the DMA, once the channel FIFO has enough data to perform a burst write or single write transaction, the channel requests access to the DMAW. The DMA FSM arbitrates access to the port based on priority settings. The channel writes out data from the FIFO in burst or single transactions based on the Write Address Sequence Mode and destination address alignment. The write process continues until the number of bytes written equals the Cell Transfer Size.
Once a cell transfer completes, the channel waits for another trigger event to start the next cell transfer. The cell transfers repeats until the number of bytes transferred equals a Block Transfer Size. If the Block Transfer Size is not an integer multiple of the Cell Transfer Size, the last cell transfer will truncate to the remaining bytes available in the block transfer.
The following figure depicts the relationship of cells and blocks and how triggers events initiate cell transfers. The DMA performs five cell transfers to complete the block transfer. The last cell transfer is truncated to match the block size.
