43.7.5 Comparator Interrupt Enable Clear (AC)

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
Table 43-6. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: INTENCLR
Offset: 0x10
Reset: 0x00000000
Property: PAC Write-Protection

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
        WIN0 
Access R/W 
Reset 0 
Bit 76543210 
       COMP1COMP0 
Access R/WR/W 
Reset 00 

Bit 8 – WIN0 Window 0 Interrupt Enable

Reading this bit returns the state of the Window 0 interrupt enable.

Writing a '0' to this bit has no effect.

Writing a '1' to this bit disables the Window interrupt.

ValueDescription
0The Window 0 interrupt is disabled.
1The Window 0 interrupt is enabled.

Bits 0, 1 – COMPx Comparator x Interrupt Enable

Reading this bit returns the state of the Comparator x interrupt enable.

Writing a '0' to this bit has no effect.

Writing a '1' to this bit disables the Comparator x interrupt.

ValueDescription
0The Comparator x interrupt is disabled.
1The Comparator x interrupt is enabled.