43.7.13 Comparator DAC Control n (AC)

Note: This register can only be written while COMPCTRLn.ENABLE =0.
Table 43-14. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: DACCTRLn
Offset: 0x38 + n*0x10 [n=0..1]
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected

Bit 3130292827262524 
 SHEN1        
Access R/W 
Reset 0 
Bit 2322212019181716 
  VALUE1[6:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 
Bit 15141312111098 
 SHEN0        
Access R/W 
Reset 0 
Bit 76543210 
  VALUE0[6:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bit 31 – SHEN1 Comparator1 DAC1 Sample and Hold Enable Operating Mode

This bit enabled the odd DAC low-power operation.

Note: If DACCTRLn.SHENn=1 user must initialize AC.CTRLC.PER and AC.CTRLC.WIDTH accordingly.
ValueDescription
0Continuous operation mode is enabled.
1Sample-and-hold operation mode is enabled.

Bits 22:16 – VALUE1[6:0] Comparator1 DAC1 Output Value

These bits define the scaling factor for odd DAC channel voltage reference. The output voltage, VOUT, is:

VOUT=AVDD(VALUE)128

Bit 15 – SHEN0 Comparator0 DAC0 Sample and Hold Enable Operating Mode

This bit enabled the even DAC low-power operation.

Note: If DACCTRLn.SHENn=1 user must initialize AC.CTRLC.PER and AC.CTRLC.WIDTH accordingly.
ValueDescription
0Continuous operation mode is enabled.
1Sample-and-hold operation mode is enabled.

Bits 6:0 – VALUE0[6:0] Comparator0 DAC0 Output Value

These bits define the scaling factor for even DAC channel voltage reference. The output voltage, VOUT, is:

VOUT=AVDD(VALUE)128

These bits can be written only while COMPCTRL(2n).ENABLE is zero.