43.7.11 Comparator Synchronization Busy (AC)

Table 43-12. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: SYNCBUSY
Offset: 0x28
Reset: 0x00000000
Property: -

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
      WINCTRL0   
Access R 
Reset 0 
Bit 76543210 
     COMPCTRL1COMPCTRL0ENABLESWRST 
Access RRRR 
Reset 0000 

Bit 10 – WINCTRL0 WINCTRL0 Synchronization Busy

This bit is cleared when the synchronization of the WINCTRL register between the clock domains is complete.

This bit is set when the synchronization of the WINCTRL register between clock domains is started.

Bits 2, 3 – COMPCTRLn COMPCTRLn Synchronization Busy (n=0,1)

This bit is cleared when the synchronization of the COMPCTRLn register between the clock domains is complete.

This bit is set when the synchronization of the COMPCTRLn register between clock domains is started.

Bit 1 – ENABLE Enable Synchronization Busy

This bit is cleared when the synchronization of the CTRLA.ENABLE bit between the clock domains is complete.

This bit is set when the synchronization of the CTRLA.ENABLE bit between clock domains is started.

Bit 0 – SWRST Software Reset Synchronization Busy

This bit is cleared when the synchronization of the CTRLA.SWRST bit between the clock domains is complete.

This bit is set when the synchronization of the CTRLA.SWRST bit between clock domains is started.