14.5.4 Single Error Correction (SEC) Error Logging
When an ECC single bit error occurs during a read from the ITCM or DnTCM (n = 0, 1) a capture address request will be performed and a retry sent to the CPU. If the address request was not spurious but intended for the TCM the address will match from previous address capture read, the corrected data will be furnished to the CPU, written back to the SRAM and single bit error interrupt (if enabled) issued.
The module on the retry Address Match will set the corresponding flags status bits in the INTFLAG register.
- For a ITCM SEC event, INTFLAG.ISERR will be set
- For a DnTCM SEC event, INTFLAG.DnSERR will be set
Note: When a SEC is detected, after capture
of the error, the module allows writes to the TCM, allowing the application to write
back to the same address the correct word with ECC calculated by the module to remove
the SEC condition for subsequent reads.