21.6.4 Clock Divide n Register

Important: To facilitate the use of sleep modes, the following conditions must be met:

PLL0 must be dedicated to the CPU.
PLL0 must be stepped down in <= 75 MHz increments to <= 75 MHz output when entering sleep modes.
PLL0 must be stepped up to the operating frequency in <= 75 MHz increments after exiting sleep modes.
The step delay for both of these processes needs to be >= 1 us.

Note:

The CLKDIV0.DIV bit field is write protected.
To ensure correct operation, frequencies must be selected so that CLKDIV0.DIV < CLKDIV1.DIV.
Frequencies must never exceed the specified maximum frequency for each clock domain.
The user updates to this register may not take effect immediately. The MCLK module logic will wait for the falling edge of the previous clock and the new clock to coincide before switching. The INTFLAG.CKRDY can be used to determine when MCLK has made the switch.

Table 21-5. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Bits 7:0 – DIV[7:0] CPU Clock Domain Division Factor

These bits define the division ratio of the main clock (MCLK) prescaler related to the CPU Clock Domain controlled by the CLKDIVn register.

Note: All other values are reserved or invalid.