21.6.3 Interrupt Flag Status and Clear
Note: Subsequent to an interrupt flag being cleared, the flag must be read back to verify
the clear before exiting the ISR. Failure to do this can result in duplicate interrupts.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | INTFLAG |
| Offset: | 0x08 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CKRDY | |||||||||
| Access | HS/K | ||||||||
| Reset | 0 |
Bit 0 – CKRDY Clock Ready Interrupt Flag
Note:
- Writing a '1' to this bit will clear the Clock Ready Interrupt Enable bit and the corresponding interrupt request.
- This flag is set by hardware when the system clocks have frequencies as indicated in the CLKDIVx registers and will generate an interrupt if CKRDY interrupt enable is set to '1'.
| Value | Description |
|---|---|
| 0 | The Clock Ready interrupt is disabled. |
| 1 | The Clock Ready interrupt is enabled. |