PIC32CZ CA80/CA90 Family

21.6.6 Peripheral BUS Clock Enable Mask1 Register

Note: AHB = Advanced High-performance Bus

APB = Advanced Peripheral Bus

AXI = Advanced eXtensible Interface

Table 21-7. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	CLKMSK1
Offset:	0x40
Reset:	0x3FFFFFFF
Property:	PAC Write-Protection


Bit	31	30	29	28	27	26	25	24
			MSK29	MSK28	MSK27	MSK26	MSK25	MSK24
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			1	1	1	1	1	1


Bit	23	22	21	20	19	18	17	16
	MSK23	MSK22	MSK21	MSK20	MSK19	MSK18	MSK17	MSK16
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	1	1	1	1	1	1	1	1


Bit	15	14	13	12	11	10	9	8
	MSK15	MSK14	MSK13	MSK12	MSK11	MSK10	MSK9	MSK8
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	1	1	1	1	1	1	1	1


Bit	7	6	5	4	3	2	1	0
	MSK7	MSK6	MSK5	MSK4	MSK3	MSK2	MSK1	MSK0
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	1	1	1	1	1	1	1	1

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29 – MSKn Clock Enable Mask


Bit Number	Description
0	SERCOM1
1	SERCOM2
2	SERCOM3
3	SERCOM4
4	SERCOM5
5	SERCOM6
6	SERCOM7
7	SERCOM8
8	SERCOM9
9	TCC0
10	TCC1
11	TCC2
12	TCC3
13	TCC4
14	TCC5
15	TCC6
16	TCC7
17	TCC8
18	TCC9
19	ADC
20	AC
21	PTC
22	I2S2
23	I2S1
24	CAN0
25	CAN1
26	CAN2
27	CAN3
28	CAN4
29	CAN5

Value	Description
0	Interrupt is disabled.
1	Interrupt is enabled.

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