24.8.4 Interrupt Enable Clear in COUNT16 mode (CTRLA.MODE=1)

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Table 24-23. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: INTENCLR
Offset: 0x08
Reset: 0x0000
Property: PAC Write-Protection

Bit 15141312111098 
 OVFTAMPER  CMP3CMP2CMP1CMP0 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 76543210 
 PER7PER6PER5PER4PER3PER2PER1PER0 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 15 – OVF Overflow Interrupt Enable

Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Overflow Interrupt Enable bit, which disables the Overflow interrupt.
ValueDescription
0The Overflow interrupt is disabled.
1The Overflow interrupt is enabled.

Bit 14 – TAMPER Tamper Interrupt Enable

Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Tamper Interrupt Enable bit, which disables the Tamper interrupt.
ValueDescription
0The Tamper interrupt is disabled.
1The Tamper interrupt is enabled.

Bits 8, 9, 10, 11 – CMPn Compare n Interrupt Enable [n = 3..0]

Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Compare n Interrupt Enable bit, which disables the Compare n interrupt.
ValueDescription
0The Compare n interrupt is disabled.
1The Compare n interrupt is enabled.

Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERn Periodic Interval n Interrupt Enable [n = 7..0]

Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Periodic Interval n Interrupt Enable bit, which disables the Periodic Interval n interrupt.
Note: The PER5, PER6, and PER7 bits are not available on 100 pin packages and 144 pin TFBGA, (RTC_IN[5:7] and RTC_OUT[5:7]).
ValueDescription
0Periodic Interval n interrupt is disabled.
1Periodic Interval n interrupt is enabled.