24.8.14 Tamper Control

Table 24-33. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: TAMPCTRL
Offset: 0x60
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected

Bit 3130292827262524 
 DEBNC7DEBNC6DEBNC5DEBNC4DEBNC3DEBNC2DEBNC1DEBNC0 
Access  
Reset 00000000 
Bit 2322212019181716 
 TAMLVL7TAMLVL6TAMLVL5TAMLVL4TAMLVL3TAMLVL2TAMLVL1TAMLVL0 
Access  
Reset 00000000 
Bit 15141312111098 
 IN7ACT[1:0]IN6ACT[1:0]IN5ACT[1:0]IN4ACT[1:0] 
Access  
Reset 00000000 
Bit 76543210 
 IN3ACT[1:0]IN2ACT[1:0]IN1ACT[1:0]IN0ACT[1:0] 
Access  
Reset 00000000 

Bits 24, 25, 26, 27, 28, 29, 30, 31 – DEBNCn Debounce Enable of Tamper Input INn [n=0..7]

Note: Debounce feature does not apply to the Active Layer Protection mode (TAMPCTRL.INACT = ACTL).
ValueDescription
0Debouncing is disabled for Tamper input INn
1Debouncing is enabled for Tamper input INn

Bits 16, 17, 18, 19, 20, 21, 22, 23 – TAMLVLn Tamper Level Select of Tamper Input INn [n=0..7]

Note: Tamper Level feature does not apply to the Active Layer Protection mode (TAMPCTRL.INACT = ACTL).
ValueDescription
0A falling edge condition will be detected on Tamper input INn.
1A rising edge condition will be detected on Tamper input INn.

Bits 0:1, 2:3, 4:5, 6:7, 8:9, 10:11, 12:13, 14:15 – INnACT Tamper Channel n Action [n=0..7]

These bits determine the action taken by Tamper Channel n.
ValueNameDescription
0x0OFFOff (Disabled)
0x1WAKEWake and set Tamper flag
0x2CAPTURECapture timestamp and set Tamper flag
0x3ACTLCompare RTC signal routed between INn and OUT pins . When a mismatch occurs, capture timestamp and set Tamper flag