31.2.23.4 NVM Interrupt Enable Set Register

Table 31-7. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: INTENSET
Offset: 0x0010
Reset: 0x00000000
Property: PAC Write-Protection

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
   WRERRRSTERR     
Access R/WR/W 
Reset 00 
Bit 76543210 
 SECERROPERRWPERRBUSERRFIFOERRCFGERRKEYERRDONE 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 13 – WRERR Write Error Interrupt Enable Bit

Writing a '0' to this bit has no effect.

Writing a 1 to this bit will enable the Write Error as an interrupt request.

Reading this bit returns whether this interrupt is enabled (=1 > enabled).

Note: This field can only be modified when STATUS.BUSY=0.

Bit 12 – RSTERR Reset or Brown Out Detect Error Interrupt Enable Bit

Writing a '0' to this bit has no effect.

Writing a 1 to this bit will enable the Reset or Brown Out Detect Error as an interrupt request.

Reading this bit returns whether this interrupt is enabled (=1 > enabled).

Note: This field can only be modified when STATUS.BUSY=0.

Bit 7 – SECERR Security Violation Error Interrupt Enable Bit

Writing a '0' to this bit has no effect.

Writing a 1 to this bit will enable the Security Violation Error as an interrupt request.

Reading this bit returns whether this interrupt is enabled (=1 > enabled).

Note: This field can only be modified when STATUS.BUSY=0.

Bit 6 – OPERR NVMOP Error Interrupt Enable Bit

Writing a '0' to this bit has no effect.

Writing a 1 to this bit will enable the NVMOP Error as an interrupt request.

Reading this bit returns whether this interrupt is enabled (=1 > enabled).

Note: This field can only be modified when STATUS.BUSY=0.

Bit 5 – WPERR Write Protection Error Interrupt Enable Bit

Writing a '0' to this bit has no effect.

Writing a 1 to this bit will enable the Write Protection Error as an interrupt request.

Reading this bit returns whether this interrupt is enabled (=1 > enabled).

Note: This field can only be modified when STATUS.BUSY=0.

Bit 4 – BUSERR AHB Bus Error During Row Write Interrupt Enable Bit

Writing a '0' to this bit has no effect.

Writing a 1 to this bit will enable the AHB Bus Error During Row Write as an interrupt request.

Reading this bit returns whether this interrupt is enabled (=1 > enabled).

Note: This field can only be modified when STATUS.BUSY=0.

Bit 3 – FIFOERR FIFO Underrun During Row Write Interrupt Enable Bit

Writing a '0' to this bit has no effect.

Writing a 1 to this bit will enable the FIFO Underrun During Row Write as an interrupt request.

Reading this bit returns whether this interrupt is enabled (=1 > enabled).

Note: This field can only be modified when STATUS.BUSY=0.

Bit 2 – CFGERR Configuration Error Interrupt Enable Bit

Writing a '0' to this bit has no effect.

Writing a 1 to this bit will enable the Configuration Error as an interrupt request.

Reading this bit returns whether this interrupt is enabled (=1 > enabled).

Note: This field can only be modified when STATUS.BUSY=0.

Bit 1 – KEYERR Key Error Interrupt Enable Bit

Writing a '0' to this bit has no effect.

Writing a 1 to this bit will enable the Key Error as an interrupt request.

Reading this bit returns whether this interrupt is enabled (=1 > enabled).

Note: This field can only be modified when STATUS.BUSY=0.

Bit 0 – DONE NVM Operation Done Interrupt Enable Bit

Writing a '0' to this bit has no effect.

Writing a 1 to this bit will enable the NVM Operation Done as an interrupt request.

Reading this bit returns whether this interrupt is enabled (=1 > enabled).

Note: This field can only be modified when STATUS.BUSY=0.