31.2.23.4 NVM Interrupt Enable Set Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | INTENSET |
| Offset: | 0x0010 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| WRERR | RSTERR | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SECERR | OPERR | WPERR | BUSERR | FIFOERR | CFGERR | KEYERR | DONE | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 13 – WRERR Write Error Interrupt Enable Bit
Writing a '0' to this bit has no effect.
Writing a 1 to this bit will enable the Write Error as an interrupt request.
Reading this bit returns whether this interrupt is enabled (=1 > enabled).
Bit 12 – RSTERR Reset or Brown Out Detect Error Interrupt Enable Bit
Writing a '0' to this bit has no effect.
Writing a 1 to this bit will enable the Reset or Brown Out Detect Error as an interrupt request.
Reading this bit returns whether this interrupt is enabled (=1 > enabled).
Bit 7 – SECERR Security Violation Error Interrupt Enable Bit
Writing a '0' to this bit has no effect.
Writing a 1 to this bit will enable the Security Violation Error as an interrupt request.
Reading this bit returns whether this interrupt is enabled (=1 > enabled).
Bit 6 – OPERR NVMOP Error Interrupt Enable Bit
Writing a '0' to this bit has no effect.
Writing a 1 to this bit will enable the NVMOP Error as an interrupt request.
Reading this bit returns whether this interrupt is enabled (=1 > enabled).
Bit 5 – WPERR Write Protection Error Interrupt Enable Bit
Writing a '0' to this bit has no effect.
Writing a 1 to this bit will enable the Write Protection Error as an interrupt request.
Reading this bit returns whether this interrupt is enabled (=1 > enabled).
Bit 4 – BUSERR AHB Bus Error During Row Write Interrupt Enable Bit
Writing a '0' to this bit has no effect.
Writing a 1 to this bit will enable the AHB Bus Error During Row Write as an interrupt request.
Reading this bit returns whether this interrupt is enabled (=1 > enabled).
Bit 3 – FIFOERR FIFO Underrun During Row Write Interrupt Enable Bit
Writing a '0' to this bit has no effect.
Writing a 1 to this bit will enable the FIFO Underrun During Row Write as an interrupt request.
Reading this bit returns whether this interrupt is enabled (=1 > enabled).
Bit 2 – CFGERR Configuration Error Interrupt Enable Bit
Writing a '0' to this bit has no effect.
Writing a 1 to this bit will enable the Configuration Error as an interrupt request.
Reading this bit returns whether this interrupt is enabled (=1 > enabled).
Bit 1 – KEYERR Key Error Interrupt Enable Bit
Writing a '0' to this bit has no effect.
Writing a 1 to this bit will enable the Key Error as an interrupt request.
Reading this bit returns whether this interrupt is enabled (=1 > enabled).
Bit 0 – DONE NVM Operation Done Interrupt Enable Bit
Writing a '0' to this bit has no effect.
Writing a 1 to this bit will enable the NVM Operation Done as an interrupt request.
Reading this bit returns whether this interrupt is enabled (=1 > enabled).