37.10.3 Endpoint0 Operating Speed Registers
This register defines the speed of the Endpoint 0.
Symbol | Description | Symbol | Description | Symbol | Description |
---|---|---|---|---|---|
R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
K | Write to clear | S | Software settable bit | — | — |
Name: | TYPE0 |
Offset: | 0x101A |
Reset: | 0x0000 |
Property: | PAC Write-Protection |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
SPEED[1:0] | |||||||||
Access | R/W | R/W | |||||||
Reset | 0 | 0 |
Bits 7:6 – SPEED[1:0] Operating Speed Control bits.
Value | Description |
---|---|
11 | Low-Speed |
10 | Full-Speed |
01 | Hi-Speed |
00 | Reserved |