42.6.11 Idle and Standby Sleep Mode Operation

The host device supports several modes of operation, starting at Active and ending with Off:

Mode of Operation: Behavior: Wake-Up Signal:
ActiveCPU running.

All memory is active.

ADC can run.

None
(CPU) IdleCPU halted.

All memory is active.

ADC (1)

All Interrupts
StandbyAll logic content retained.

ADC (1)

NVM in sleep mode.

Configurable RAM retention support.

All Interrupts
HibernateOnly backup domain remains active.

ADC cannot run.

Configurable RAM retention.

Only 32 kHz clock can run.

Backup Interrupts
BackupOnly backup domain remains active.

ADC cannot run.

Only 32 kHz clock can run.

Backup Interrupts
OffEverything is off.External Reset
Note:
  1. The CTRLA.ONDEMAND and CTRLA.RUNSTDBY bits control the behavior of the ADC during Idle and Standby sleep modes, in cases where the ADC is enabled (CTRLA.ENABLE = 1). See the following table:
Table 42-5. ADC Idle and Standby Mode Behavior
CTRLA.ENABLECTRLA.RUNSTDBYCTRLA.ONDEMANDDescription
0xxDisabled.
100ADC inactive in Idle and Standby mode
101Run in Idle and Standby modes only on EVSYS trigger request.
110Run in Idle and Standby modes.
111Run in Idle and Standby modes.
Note: When CTRLA.ONDEMAND=1, the analog block is always powered-off. When a start request is detected, the system returns from sleep and starts a new conversion. When RUNSTDBY is enabled the GCLK to the ADC continues to run when ONDEMAND=0. With ONDEMAND and RUNSTDBY set the GCLK will be requested. Therefore, there will be an additional delay until the analog front end is ready (CTLINTFLAG.CRRDYn=1).