47.5.6 SPIXBUF Register Operation

In standard buffer mode, the transmit buffer and receive buffer are each one element deep. Writes to the SPIxBUF are clocked in to the SPIxTXB register. Reads to the SPIBUF are read out of the SPIxRXB register. The data from these registers is not synchronized. As a consequence of this, the CPU must never read out of this register (SPIxBUF) until the SPIRBF is set, and must never write to this register until the SPITBF is cleared.

The buffer mode, a multi-element FIFO synchronizes data between the CPU clock domain and the SCK domain. The FIFO depth is always 64 bytes deep. AUDWD_MODE[1:0] field selects 32(24,20)-bit data lengths. If AUDWD_MODE selects 16-bit data lengths. If AUDWD_MODE selects 8-bit data lengths.

The SPIxBUF provides access for both the Rx FIFO and the Tx FIFO. CPU reads complete from the Rx FIFO and CPU writes complete into the Tx FIFO. There is no protection (status of an error) against reading an empty Rx FIFO or writing a full Tx FIFO. However, the SPI Shift Register (SPIxSR) provides Transmit Under-run (SPITUR) and Receive Overflow (SPIROV) status.

The SPI provides four status flags for determining the state of Tx and Rx data in the FIFOS and SPIxSR. The SPIxSTAT.SPIBUSY bit indicates the SPIxSR is sending/receiving data or copying data to/from a FIFO. The SPIxSTAT.SRMT indicates if the SPIxSR is empty or not.

When configured for non-framed, client mode with CPHA = 1, the SPI must drive the first bit of data on SDA with out using SCK. Therefore, the first bit of data is driven directly from the SPIxTXB and the second and subsequent bits from the SPIxSR. This condition causes asynchronous interaction with the SPIxTXB. When software can keep up with the selected data transfer rate of the SPI, the first bit of data is driven out of the SPIxTXB has plenty of setup time.

However, if software cannot fully keep up with the configured transfer rate causing the SPIxTXB to be empty at the start of a transaction one of two things can happen. If the SPIxTXB stays empty until after the first bit transmits, the SPI transmits the previous data. If data arrives in the SPIxTXB during the first bit time, the SPIxTXB drives the first bit on SDA and pushes the data into the SPIxSR. When the SPIxTXB becomes not empty during the first bit time, the first bit cannot be guaranteed to meet setup time.

To ensure this case does not cause issues, software needs to keep up with the selected transfer rate.