47.5.11 Host Mode Clocking

The SPI macro has a 13-bit baud rate generator to allow flexibility in baud rate generation. The SPIxBRG register is readable and writable and determines the baud rate. The GCLK_IxS provided to the peripheral is a divider function of the CPU core clock. This clock can then again be divided, based on the value loaded in the SPIxBRG register, before it is provided to the external devices via the SCK pin. The SCK clock is of 50% duty cycle. Some sample SPI clock frequencies are shown in Sample SCK Frequencies.