47.5.1 SPI Data Transmission/Reception

Control bits SPIxCTRL_*.MODE[32,16] allow the peripheral to communicate in either 8-bit (both MODE32 and MODE16 are cleared), 16-bit (MODE16 is set) or 32-bit (MODE32 is set) mode (See the following table). The functionality is the same for each mode except for the number of bits received and transmitted.

Table 47-1. Communication Mode Selection
MODE32MODE16MODE_ENCOMMUNICATION
0008-bit
01016-bit
10032-bit
11032-bit

Additionally, the following should be noted in this context:

  • Data is transmitted through and received by SPIxSR
    • In 8-bit operation, data is transmitted from bit7
    • In16-bit operation, data is transmitted from bit 15
    • In32-bit operation, data is transmitted from bit 31
    • In all modes, data is not have a SHIFT register but a register that fills MSB first and MSB-1 till end
  • A series of eight, sixteen, or thirty-two clock pulses send out 8/16/32 bits from the SPIxSR to the SDO pin and simultaneously store in 8/16/32-bit data from the SDI pin. An event is generated when the transfer is complete.

16/32-bit (0/1) operation is identical to 8-bit operation except that the number of bits transmitted is sixteen or thirty-two, instead of eight.

Once the peripheral is enabled (SPIxCTRL_*.ENABLE) and set up for Host mode of operation, transmission/reception will start as soon as the data is written to SPIxBUF, thereby loading the SPIxTXB register, and the transmit buffer empty status flag (SPIxSTAT.SPITBE) is cleared. This flag will automatically be set in hardware after the data is transferred from SPIxTXB to SPIxSR. Now, the data to be transmitted next can be loaded into the SPIxTXB register at any time as long as the SPIxSTAT.SPITBE bit is set. The write can occur while SPIxSR is sending the previously written data, allowing continuous transmission. When the host/client transfer finishes, the data received is moved from SPIxSR to SPIxRXB and the receive buffer full status flag (SPIxSTAT.SPIRBF) is set. This flag will automatically be cleared in hardware after the data received is read by the user software.

Note: The SPIxSR register cannot be directly written to by the user. All writes to this register are performed via the SPIxBUF register.

In Host mode, the APBm_clk is divided based on the value loaded into SPIxBRG[12:0] and then output via SCK pin to the client devices.

In Client mode, data is received and transmitted as external clock pulses appear on SCK pin and the interrupt event will be generated as the last bit of the receive data is latched.