31.3.12.3 Single Error Corrected (SERR)

When ECC is active (i.e. not OFF/Bypass) and a read from Flash memory results in an ECC Single Error Corrected (SEC), the FCR reports it via an interrupt since it is not a critical error. Data in the read buffer is correct and no further ECC events are generated for reads that hit the buffer as long as that data is in the buffer.

Each read of the Flash that results in an SEC causes the FCR to set INTFLAG.SERR when ECCCTRL.SECCNT = 0. If the count in SECCNT is non-zero, the FCR decrements it and does not set SERR. The FCR does not reload SECCNT when it is zero. Software must write the desired count each time it services the SEC interrupt event.

When Dynamic ECC is active, an SERR can be caused by a bit error in CTL. If this is the case, a DERR and an SERR can be caused by the same read.