31.3.12.1 ECCCTRL SFR Description

ECCUNLCK

The ECC mode of the Flash can be locked for the duration of the program lifetime in Flash. When FECCUNLCK is 0, ECCUNLCK is also 0 and the selected ECC mode cannot be changed until Flash is updated. This option prevents undesired changing of the mode. When FECCUNLCK is 1 (the default erased state of the flash), ECCUNLCK and ECCCTL can be modified.

Note: If ECCUNLCK is 0, debug mode cannot override the ECC or error reporting via DBGCTRL.

ECCCTRL

The field ECCCTL determines how the parity bits are used for Flash reads and writes. The four options, ECC, Dynamic, Dynamic w/o Bus Error and Bypass affect reads and writes differently.

For all ECC modes, writes to the Flash update the Flash ECC Control Bits, CTL[2:0], which store whether ECC or Simple Parity was calculated on the data. The Control Bits exists per Flash word (256-bit data). If the FCW performs a Single Write then the CTL is written with 3’b111 (i.e. not changed from the default erase value of the bits) for Parity. If the FCW performs a Quad Write then the CTL is written as 3’b000 for ECC. CTL[2:0] must be 3’b111 for Single Writes using Simple Parity since all Flash ECC Control Bits (CTL) are not updated with a Single Write. CTL[2:0] is updated for Quad Writes so 3’b000 works for selecting ECC.

The ECC Control Bits table shows the allowed operations based on ECCCTL and its effect on the CTL[2:0] field.

ECC Writes with ECC Reads

If ECCCTL[1:0]= 2’b00, ECC hardware is always active. This mode is also referred to as ECC On.

Only Quad Write programming is allowed in this mode, which always calculates and stores ECC values for the data. The FCW disables the Single Write Program command by making it a no-op if an attempt is made to execute it. Note Row Write uses multiple Quad Writes for programming.

Reads in this mode ignore Flash ECC Control bits CTL[2:0] and always perform ECC error checking and correction. This mode can generate ECC SEC events or ECC DED events.

Note: The FCR forces ECC to be enabled for all calibration word reads during the reset sequence.

Dynamic Writes with Dynamic Reads

If ECCCTL[1:0]= 2’b01, ECC hardware dynamically switches between ECC and Parity. This mode is also referred to as Dynamic ECC.

Both Quad Write and Single Write programming are allowed in this mode.

Reads in this mode obey Flash ECC Control bits CTL[2:0] to determine whether ECC or Parity is calculated on the data. This mode can generate ECC SEC events, and ECC DED events, and Parity Errors that are reported via the ECC DED event path.

Note that Flash ECC Control bits CTL[2:0] uses a majority detect during reads to make it tolerant to single bit failures. A single bit failure of CTL[2:0] is reported via the ECC SEC event path, and only occurs in this mode. If an ECC SEC occurs at the same time as a CTL SEC, the error is reported on ECC SEC event path since both single bit failures get corrected. They also only count as one error with respect to SECCNT.

Dynamic Writes with Dynamic Reads but w/o Bus Error (for DED or Parity)

If ECCCTL[1:0]= 2’b10, ECC hardware dynamically switches between ECC and Parity. However, Neither DED nor Parity Errors cause a Bus Error. The DERR bit is still set for uncorrectable errors. Otherwise, this mode behaves the same as in Dynamic Writes with Dynamic Reads, above.

Dynamic Writes with No Error Checks

If ECCCTL[1:0] = 2’b11, ECC hardware is bypassed (for reads). This mode is also referred to as ECC Bypass.