39.7.9 Coding Timing Parameters
All timing parameters are defined for one chip select and are grouped together in one register according to their type.
The SMC SETUP register groups the definition of all setup parameters:
- NRDSETUP
- NCS RDSETUP
- NWE SETUP
- NCS WR SETUP
The SMC PULSE register groups the definition of all pulse parameters:
- NRDPULSE
- NCS RDPULSE
- NWE PULSE
- NCS WR PULSE
The SMC CYCLE register groups the definition of all cycle parameters:
- NRDCYCLE
- NWE CYCLE
The following table shows how the timing parameters are coded and their permitted range.
| Coded Value | Number of Bits | Effective Value | Permitted Range | |
|---|---|---|---|---|
| Coded Value | Effective Value | |||
| setup [5:0] | 6 | 128 x setup[5] + setup[4:0] | 0 :: 31 | 0 :: 128+31 |
| pulse [6:0] | 7 | 256 x pulse[6] + pulse[5:0] | 0 :: 63 | 0 :: 256+63 |
| cycle [8:0] | 9 | 256 x cycle[8:7] + cycle[6:0] | 0 :: 127 | 0 :: 256+127 |
| 0 :: 512+127 | ||||
| 0 :: 768+127 | ||||