31.3.10.14 CRCPAUSE SFR Description

The PAUSE bit halts CRC reads of Flash memory. The CRC FSM only checks the PAUSE bit when the PERIOD counter (being zero) triggers a read. The counter and the LFSR do not pause. When the FSM exits pause with the counter being zero, it requests a read of Flash to feed the LFSR.

Software set and clear of the PAUSE bit may occur without causing the FSM to actually pause operation. This type of interaction can occur during the time that the PERIOD counter is non-zero.