1.3.1 Design Implementation

The following figure shows the Libero SoC software design implementation of the TVS demo design.

Figure 1-2. TVS Demo Design

The top-level design includes the following components:

  • TVS_IP_0 Macro
  • Core_UART_0
  • TVS_to_UART_0 logic
  • clock_gen_0
  • INIT_MONITOR_0 and PF_RESET_0