29.4.2 Programmable Edge Detectors

The output of each of the 16 input selection latches are fed into programmable edge detectors. The edge detectors are by default positive edge-triggered, but can be programmed to be negative edge-triggered or bypassed completely.

The edge detectors are positive-edge triggered. If the application requires negative-edge detection, bit zero of the CLB Input Synchronizer latches must be set (CLB Input Synchronizer[0] = '1'). The output of the synchronizer latches will be synchronized to the CLB clock.

If the edge detectors are bypassed, the input signal is fed directly to the CLB without synchronization.

Important: If any of the BLEs are programmed to use its output flop, care must be taken so that the unsynchronized input does not cause the BLE flop to go into metastability.

Figure 29-4. Edge Detector Operation when CLB Input Synchronizer[2:0] = '00X'

Figure 29-5. Edge Detector Operation when CLB Input Synchronizer[2:0] = '010'

Figure 29-6. Edge Detector Operation when CLB Input Synchronizer[2:0] = '011'

Figure 29-7. Edge Detector Operation when CLB Input Synchronizer[2:0] = '10X'

Figure 29-8. Edge Detector Operation when CLB Input Synchronizer[2:0] = '110'

Figure 29-9. Edge Detector Operation when CLB Input Synchronizer[2:0] = '111'