29.6 CLB Clock Selection

The CLB module clock source can be selected using the CLB Clock Selection (CLBCLK) register. Available clock sources include internal signals from select oscillator or timer resources, and external sources such as crystal oscillators. Additionally there are four CLB PPS inputs that can be used as clock sources to the module.

The Configuration Interface provides clock divider selections which can be configured through the CLB Clock Divider selection latches.

The output of the clock divider circuit (BLE_clk) is connected to all 32 BLE output flops, the 3-bit counter, and as a clock source to the CLBSWIN registers.