12.10.12 PIR2
Note: Interrupt flag bits are set when an
Interrupt condition occurs, regardless of the state of its corresponding enable bit or
the Global Enable (GIE) bit. User software may ensure the appropriate interrupt flag
bits are cleared before enabling an interrupt.
| Name: | PIR2 |
| Offset: | 0x008E |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CCP2IF | CCP1IF | TMR2IF | |||||||
| Access | R/W/HS | R/W/HS | R/W/HS | ||||||
| Reset | 0 | 0 | 0 |
Bit 6 – CCP2IF CCP2 Interrupt Flag
| Value | CCP Mode | ||
|---|---|---|---|
| Capture | Compare | PWM | |
1 | Capture occurred (must be cleared in software) | Compare match occurred (must be cleared in software) | Output trailing edge occurred (must be cleared in software) |
0 | Capture did not occur | Compare match did not occur | Output trailing edge did not occur |
Bit 5 – CCP1IF CCP1 Interrupt Flag
| Value | CCP Mode | ||
|---|---|---|---|
| Capture | Compare | PWM | |
1 | Capture occurred (must be cleared in software) | Compare match occurred (must be cleared in software) | Output trailing edge occurred (must be cleared in software) |
0 | Capture did not occur | Compare match did not occur | Output trailing edge did not occur |
Bit 2 – TMR2IF TMR2 Interrupt Flag
| Value | Description |
|---|---|
| 1 | TMR2 interrupt has occurred (must be cleared in software) |
| 0 | TMR2 interrupt event has not occurred |