12.10.15 PIR5

Peripheral Interrupt Request Register 5
Note: Interrupt flag bits are set when an Interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable (GIE) bit. User software may ensure the appropriate interrupt flag bits are cleared before enabling an interrupt.
Name: PIR5
Offset: 0x0091

Bit 76543210 
 CM2IFCM1IF  BCL1IFSSP1IF   
Access R/W/HSR/W/HSR/W/HSR/W/HS 
Reset 0000 

Bit 7 – CM2IF Comparator 2 Interrupt Flag

ValueDescription
1 Comparator 2 interrupt has occurred (must be cleared in software)
0 Comparator 2 interrupt event has not occurred

Bit 6 – CM1IF Comparator 1 Interrupt Flag

ValueDescription
1 Comparator 2 interrupt has occurred (must be cleared in software)
0 Comparator 2 interrupt event has not occurred

Bit 3 – BCL1IF MSSP1 Bus Collision Interrupt Flag

ValueDescription
1 An MSSP1 Bus Collision was detected (must be cleared in software)
0 No MSSP1 Bus Collision event was detected

Bit 2 – SSP1IF MSSP1 Interrupt Flag

ValueDescription
1 MSSP1 interrupt has occurred (must be cleared in software)
0 MSSP1 interrupt event has not occurred
Interrupt flag bits are set when an Interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable (GIE) bit. User software may ensure the appropriate interrupt flag bits are cleared before enabling an interrupt.