29.9.6 CLBCLK

CLB Clock Selection

Name:	CLBCLK
Offset:	0x0515


Bit	7	6	5	4	3	2	1	0
					CLK[3:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0

Bits 3:0 – CLK[3:0] CLB Clock Selection

Table 29-4. CLBCLK Clock Selections
CLK	Clock Source
`1111`	Reserved
`1110`	TMR2_postscaled_OUT
`1101`	TMR1_overflow_OUT
`1100`	TMR0_overflow_OUT
`1011`	ADCRC
`1010`	EXTOSC
`1001`	MFINTOSC (32 kHz)
`1000`	MFINTOSC (500 kHz)
`0111`	LFINTOSC
`0110`	HFINTOSC
`0101`	F_OSC
`0100`	CLBIN3PPS
`0011`	CLBIN2PPS
`0010`	CLBIN1PPS
`0001`	CLBIN0PPS
`0000`	No clock selected

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