1.5 Reset
(Ask a Question)DEVRST_N or device reset is a dedicated device reset input pad, powered through the dedicated I/O bank. The DEVRST_N pad connects to the reset ports of all the hard blocks on the device through hardwired connections. The DEVRST_N assertion results in full re-initialization of the device, including the loading of user configuration data to PCIe, transceivers, and the re-initialization of fabric LSRAMs and µSRAMs.
For designing a robust system, users may use the dedicated DEVRST_N pin or a general purpose reset signal using any GPIO/HSIO as a global system level reset.
For the following cases, users may use the DEVRST_N as a warm reset for the device:
- A user design modifies auto-initialized fabric RAMs or PCIe configuration during operation.
- A user design is using PCIe, transceivers, or user crypto.
For all other use cases, it is recommended to use a general purpose reset signal using any GPIO/HSIO IO, because they take much shorter time for design to come out of reset.
If the dedicated DEVRST_N is not used for warm resets, the DEVRST_N pin must be configured using one of the following methods:
- Drive the signal with a POR chip or an external device, and keep the DEVRST_N asserted till the system/clocks are stable and the chip is properly powered up.
- Connect DEVRST_N to VDDI3 through a 1 kΩ resistor per pin, without
sharing with any other pins.
- In this case, the user needs to ensure that all clocks going to the device are stable before the user design is released from Power-on Reset. For details on the minimum time taken for the fabric design to be activated after power-on, refer to PolarFire FPGA Datasheet (Power-Up To Functional section).