1.1 Power Supplies

(Ask a Question)

The following illustration shows the typical power supply requirements for PolarFire devices and the recommended connections of power rails when every part of the device is used in a system. For information on decoupling capacitors associated with individual power supplies, see PolarFire Decoupling Capacitors.

To calculate the number of decoupling capacitors, it is important to know the target impedance of the power plane. Target impedance is calculated as follows:

Equation 1-1. Target Impedance

Z_{M a x} = % Ripple \times \frac{V_{s u p p l y}}{I_{t r a n s}}

Where:

V_supply: Supply voltage of the power plane
% Ripple: Percentage of ripples that is allowed on the power plane. See PolarFire FPGA Datasheet for more information about ripple in Recommended Operating Conditions table.
I_trans: Transient current drawn on the power plane. The transient current is half of the maximum current. Maximum current is taken from the Microchip Power Estimator (MPE) - PolarFire, RT PolarFire and PolarFire SoC.
Zmax: Target impedance of the plane

For the device to operate successfully, power supplies must be free from unregulated spikes and the associated grounds must be free from noise. All overshoots and undershoots must be within the absolute maximum ratings provided in the PolarFire FPGA Datasheet .

The following table lists the various power supplies required for PolarFire FPGAs.

Table 1-1. Supply Pins
Name	Description
XCVR_VREF	Voltage reference for transceivers
VDD_XCVR_CLK	Power to input buffers for the transceiver reference clock
VDDA25	Power to the transceiver PLL
VDDA¹	Power to the transceiver TX and RX lanes
VSS	Core digital ground
VDD²	Device core digital supply
VDDI3 (JTAG Bank)	Power to JTAG bank pins
VDDIx (GPIO Banks)	Power to GPIO bank pins
VDDIx (HSIO Banks)	Power to HSIO bank pins
VDD25	Power to corner PLLs and PNVM
VDD18	Power to programming and HSIO auxiliary supply
VDDAUXx	Power to GPIO auxiliary supply

Note:

VDDA: This supply can be powered to 1.0V or 1.05V. For more information, see tables 4-2 in PolarFire FPGA Datasheet . This is a quiet supply for the device. One method is to use a Linear regulator to ensure the supply is quiet.
VDD: This supply can be powered to 1.0V or 1.05V. For more information, see tables 4-2 in PolarFire FPGA Datasheet .

VREFx: This is the reference voltage for DDR3 and DDR4 signals. The following VREF voltages can be generated internally and externally.

Internal VREF: This is not subjected to PCB and package inductance and capacitance loss. These changes provide the highest performance and can be programmed as required by DDR controller.
External VREF: This is fixed and cannot be programed as required. The PCB and package inductance and capacitance impact the VREF performance.

Important: If VDDI and VDDAUX need to be configured to the same voltage (2.5V or 3.3V), ensure both VDDI and VDDAUX are supplied from the same regulator. Do not use different regulators to source these rails. This prevents any voltage variations between VDDI and VDDAUX. In this case, the board must not supply the VDDI and VDDAUX from individual voltage supplies.

When a GPIO bank requires the VDDI to be less than 2.5V (1.2V, 1.5V, or 1.8V), the VDDAUX for that bank must be tied to 2.5V supply irrespective of the VDDI supply. The VDDI requires a separate supply for the specific I/O type (1.5V or 1.8V).

Important:

The on-chip Power-on Reset circuitry requires the V_DD, V_DD18, and V_DD25 supplies to ramp monotonically from 0V to the minimum recommended operating voltage.
You must initiate the I/O calibration only when both the VDDA and XCVR_VREF supplies are up.

For a detailed pin description, see PolarFire FPGA Packaging and Pin Descriptions User Guide.