1.2 I/O Glitch

A glitch might occur during power-up or power-down for GPIO/HSIO outputs in PolarFire devices. Glitch can occur before or after the device reaches a functional state. These glitches are not observed on LVDS outputs or Transceiver I/Os. No reliability issues are caused by either of the glitch types. There are three types of glitch that can occur:

  • Parasitic glitches may occur for GPIOs or HSIOs before the device reaches functional state with a maximum glitch of 1V with a 0.4 ms width. This type of glitch can typically be ignored. It is recommended to use a 100K pull-down resistor on critical signals1 of the GPIO or HSIO pins if this type of glitch cannot be ignored. No glitches are observed once mitigation recommendations are placed. This may occur for both erased/blank and programmed units.
  • Another type of glitch may occur on GPIOs and HSIOs during power-on sequencing or boot-up. This is due to a weak pull-up resistor being enabled by default on an input, output or bidirectional I/O. To mitigate this glitch, use the Libero SoC I/O Editor or PDC constraint to program a weak pull-down on the output buffer on the specified I/O. This may occur for both erased/blank and programmed units.
  • The last type of glitch may occur after the device reaches functional state and may occur for both erased/blank and programmed units. This type of glitch is related to the power-up and power-down sequence of VDDI and VDDAUX supplies. This occurs only on GPIOs where the VDDI is 1.5V or 1.8V only with a maximum glitch of 1V with a 0.8 ms width during power-up and a maximum glitch of 1.8V with a 1 ms width during power-down. For HSIOs, where the VDDI is 1.5V or 1.8V only a maximum glitch of 600 mV and 1.5 ms width may occur at Power-Up and a maximum glitch of 220 mV 200 μs width may occur at Power-Down.

To mitigate the post functional state glitch, follow the recommendations in the following table.

Table 1-11. Power Sequencing1 (For GPIO)
Use Cases for GPIOPower-up Sequencing Requirement for Mitigating Glitches2Power-down Sequencing Requirements for Mitigating Glitches2
VDDIVDDAUX
1.2V2.5VNo glitch occursNo glitch occurs
1.5V2.5VPower up VDDAUX before VDDI of that bank
  • Power down VDDI before or in concurrence with VDDAUX
  • Power down VDDI before VDD or VDD25
1.8V2.5VPower up VDDAUX before VDDI of that bank
  • Power down VDDI before or in concurrence with VDDAUX
  • Power down VDDI before VDD or VDD25
2.5V2.5VPower up VDDAUX and VDDI from the same RegulatorNo glitch occurs
3.3V3.3VPower up VDDAUX and VDDI from the same RegulatorNo glitch occurs
Table 1-12. Power Sequencing1 (For HSIO)
Use Cases for HSIOPower-up Sequencing Requirement for Mitigating Glitches2Power-down Sequencing Requirements for Mitigating Glitches2
VDDIVDD18
1.2V1.8VNo glitch occursNo glitch occurs
1.5V1.8VPower up VDD18 before VDDI of that bankPower down VDDI before VDD18, VDD, and VDD25
1.8V1.8VPower up VDD18 before VDDI of that bank3Power down VDDI before VDD18, VDD, and VDD25
Note:
  1. No glitches are observed once mitigation recommendations are placed.
  2. The preceding power sequence does not mitigate any parasitic glitches. Add a 100K pull-down resistors to critical signals of GPIO or HSIO pins for mitigation of parasitic glitches.
  3. When VDDI = 1.8V and VDD18 = 1.8V, VDDI and VDD18 must be sourced from two separate power sources to meet the power sequencing requirements described in Table 1-12. This mitigates any potential I/O glitch.
Important: A glitch might occur on GPIO pins during JTAG programming, if power is disrupted. The glitch can be mitigated by powering down VDDI before VDDAUX, VDD, and VDDI3.
1

Critical outputs like Reset or Clock of the HSIO or GPIOs going into another device.