30.3.3.6.3 Burst Accumulation
The figure below shows the timing diagram for the ADC when running in Burst Accumulation mode without using the PGA.
Note:
- If the Low Latency (LOWLAT) bit is set to ‘
1
’ in the Control A (ADCn.CTRLA) register, the analog modules in the ADC will not turn OFF at the end of the conversion, eliminating the initialization time when triggering the following conversion. - The time from the conversion has finished to the outputs are available in the registers is 0.5 CLK_ADC cycles followed by 1 CLK_MAIN cycle. The last conversion and accumulation require an additional CLK_MAIN cycle. With minimum prescaling, this sums up to 1.5 CLK_ADC cycles before the final outputs are available.