30.3.3.6 Conversion Timing

Some of the analog modules in the ADC are disabled between conversions and require time to initialize before a conversion starts. Only the modules used by the current ADC configuration are enabled, and as the initializations run in parallel, the limiting factor is the module with the slowest initialization time. The following table shows the different initialization times needed by the analog modules.

Table 30-5. ADC Initialization Timing
Analog ModuleInitialization Time
ADC10 µs(1)
PGA20 µs
Settling of internal references60 µs
Internal Tempsense input35 µs
Internal DAC input35 µs
Note:
  1. If CLK_PER < 2 MHz, the ADC initialization time is 20 CLK_PER cycles.

Example: Selecting Tempsense as input and using VDD as the reference will give a 35 µs initialization time. Using the Tempsense with the 1.024V internal reference will result in a 60 µs initialization time.

The ADC can be put in Low-Latency mode by writing a ‘1’ to the LOWLAT bit in the Control A (ADCn.CTRLA) register. This will keep the configured modules continuously enabled, effectively removing all initialization time at the start of a conversion. The initialization time is still needed when enabling the ADC for the first time, and if reconfiguring the ADC to use an input or reference that requires initialization, as shown in the table above. The ADC Busy (ADCBUSY) bit in the Status (ADCn.STATUS) register can be used to check if initialization is ongoing.

The sampling period of the input to the ADC is configured through the Sample Duration (SAMPDUR) bit field in the Control E (ADCn.CTRLE) register as (SAMPDUR + ½) CLK_ADC cycles. The input signal characteristics affect how long the sampling period has to be.

When the PGA is used, it is sampling continuously and will only be in the Hold state when the ADC is sampling the PGA. This ADC PGA Sample Duration (ADCPGASAMPDUR) depends on fCLK_ADC and is configured in the PGA Control (ADCn.PGACTRL) register. SAMPDUR will still configure the minimum sampling period of the input to the PGA as (SAMPDUR + 1) CLK_ADC cycles. In Burst mode, SAMPDUR must be ≥12, limited by the length of the Conversion state.

The Series and Burst Accumulation modes can be used for oversampling to achieve up to 5 bit higher resolution, given suitable input signal and sampling frequency. Increasing the resolution by n bits can be achieved by accumulating 4n samples and dividing the accumulated result by 2n. The Sample Accumulation Number (SAMPNUM) bit field in the Control F (ADCn.CTRLF) register can be configured for up to 45 = 1024 samples, resulting in up to 17-bit resolution.

The two tables below show the calculated conversion rates (fconv) for a subset of the possible combinations of fCLK_ADC and sample durations. For more details, see the relevant timing diagrams on the following pages.

Table 30-6. Example Conversion Rates (fconv) for fCLK_ADC = 5 MHz and ADCPGASAMPDUR = 20
SAMPDURPGAfconv(1) Single 8-bit [sps]fconv(1) Single 12-bit [sps]fconv Burst Accumulation [sps]
2OFF384615294118312500
12OFF217391185185192308
48OFF847467936580645
255OFF187971851918587
2ON149254133333N/A
12ON114943105263147059
48ON628935988071429
255ON174521721218051
Table 30-7. Example Conversion Rates (fconv) for fCLK_ADC = 333 kHz and ADCPGASAMPDUR = 6
SAMPDURPGAfconv(1) Single 8-bit [sps]fconv(1) Single 12-bit [sps]fconv Burst Accumulation [sps]
2OFF256411960820833
12OFF144931234612821
48OFF565052915376
255OFF125312351239
2ON1709414184N/A
12ON11299995016667
48ON508947965952
255ON122312061267
Note:
  1. Conversion rates with the Free-Running (FREERUN) bit set to ‘1’ in the Control F (ADCn.CTRLF) register; a new conversion will be started immediately after the results are available in the ADC.