30.3.3.6.1 Single Conversion
The figure below shows the timing diagram for the ADC when running in Single 8- or 12-bit mode without using the PGA.
Note:
- In Single 8-bit mode, the length of the Conversion state is nine CLK_ADC cycles. In all other modes, it is thirteen cycles.
- If the Low Latency (LOWLAT) bit is set to ‘
1
’ in the Control A (ADCn.CTRLA) register, the analog modules in the ADC will not turn OFF at the end of the conversion, eliminating the initialization time when triggering the following conversion. - The time from the conversion has finished to the outputs are available in the registers is 0.5 CLK_ADC cycles followed by 1 CLK_MAIN cycle. With minimum prescaling, this sums up to 1 CLK_ADC cycle.