2.5 Adding Physical Constraints Using Libero

The transceiver I/O pin assignments can be made with PDC commands and passed as physical design constraints to the physical layout tool. The I/O PDC constraints (for XCVR LANE RX pins, TX pins, and XCVR_REF_CLK pins) must be specified in an I/O PDC file. The chip plan location constraints for TXPLL must be specified in a floor plan PDC file. The I/O Editor provides a GUI tool designed to make I/O pin assignments graphically and user-friendly, as an easy alternative to writing PDC commands. When the pin assignment is committed and saved in the Pin Planner, a PDC file is created. This PDC file can then be passed to the Place and Route tool as a physical design constraint.