2.1 Libero Configurators

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Three explicit PolarFire configurators are the preferred tool for wrapper generation needed to instantiate transceiver primitive macros called PF_XCVR_REF_CLK, PF_TX_PLL, and PF_XCVR. The configurator is part of the Libero SoC design tools and is available when the PolarFire macros are downloaded from the Libero catalog.

The following table provides details on three Libero transceiver configurators in the Libero Software: transmit PLL, transceiver reference clock, and transceiver interface modules. The transmit PLL (PF_TX_PLL) and transceiver interface (PF_XCVR) modules are used when the transceivers are implemented in the Libero FPGA design. The transceiver reference clock (PF_XCVR_REF_CLK) is used when the dedicated input clock from the top-level pins are used. Optionally, this is not used if the transceiver reference clock comes from the PLL or from the FPGA fabric. The user must instantiate and configure these three blocks in their transceiver design.

Table 2-1. Transceiver Configurator Component List
Configurator	Macro	Details
Transmit PLL	PF_TX_PLL	Generates the TxPLL/TxPLL_SSC based on the provided input to the GUI. The PF_TX_PLL generates the BIT_CLK for the transceiver.
Transceiver Reference Clock	PF_XCVR_REF_CLK	Generates the reference clock based on the provided input to the GUI—selection of differential or single-end input buffer and selection of single or dual clock inputs to the transmit PLL clock interface.
Transceiver Interface	PF_XCVR_ERM	Configures the requested number of lanes (4 lane maximum) with the same PMA and PCS settings—the lanes required by the design and CDRPLL settings.

As the FPGA designer makes selections in the each transceiver module configurators, it automatically guides and narrows down the subsequent choices and defaults. Each configurator maintains a module diagram while the designer selects the module properties. Once all the choices are made, the configurator generates an RTL netlist that instantiates the required macros specific to the requirements of the design. Only the relevant ports appear in the generated macro. This section describes how to enter these configuration parameters in the transceiver configurator GUIs.