2.3 Libero Generated Files

Libero SoC software automatically generates the required files after stepping through the design entry steps of the transceiver. The following files are created:

  • Netlist file—the RTL netlist instantiates the transceiver macros and related RTL wrappers based on protocol specific functions.
  • <design name>.sdc file—Timing constraints file in the case of TXPLL and XCVR configurators.
  • <module name>.v, _syn_comps.v, _pre_comps.v
    • HDL source files for all Synthesis and Simulation tools.
    • HDL source files for Synopsys SynplifyPro Synthesis tool.
    • HDL source files for Mentor Precision Synthesis tool.
Note: The entire file list and their file paths are maintained in mainfest.txt at <Project Directory>/component/work/<Component name>/*_manifest.txt files.
Note: XCVR and PCIESS initialization data is available in the generated netlists of the TXPLL, XCVR, and PCIE blocks. This is used to configure the blocks specifically for users design customization. See Transceiver Initialization.