2.2.2 Half-Duplex Mode

Another mode of the transceiver is half-duplex mode. It is defined by allowing parts of the Rx and Tx to operate independently. Half-duplex modes optimize the use of lanes within XCVR quads by allowing the separation of Rx and Tx within a lane. To address the half-duplex modes, the following options are available to the transceiver.

• Tx only
• Rx only
• Tx and Rx (Independent)

When users select Tx only or Rx only option, then one physical XCVR lane is completely used, and the unused Rx or Tx cannot be used. When users select Rx only in the GUI, the Tx GUI options are marked as N/A for display purposes. In the same way, when users select Tx only in the GUI, the Rx GUI options are marked as N/A for display purposes. However, in both cases, the unused Tx or Rx parameters are still set to some valid values in the generated core (based on the default parameter values from the core). PMA_ARSTN resets both the Tx and Rx of the PMA, however, the PCS_ARSTN will reset the Tx only or Rx only accordingly.

If users intend to implement two independent half-duplex channels in the same physical XCVR lane then select the 'Tx and Rx (Independent)' option in Transceiver mode. By using the 'Tx and Rx (Independent)' option, users can specify a different data rate for the Rx channel and Tx channel. When configured Tx and Rx (Independent), an additional input pin (LANE#_REF_CLK) is exposed on the component. See the related port list for pin definition. Additionally, the PCS-FABRIC width can also be different between Rx and Tx. However, if half-duplex applications are to be merged into one XCVR lane, then both applications must use the same basic mode of the PCS. The reason for this is, system register control for steering the data path among the four basic modes (PIPE, 64B6xB, 8B10B, NATIVE/PMA) is shared for Tx and Rx.

Libero SoC programs the appropriate registers within the transceiver to power down the serializer or de-serializer in Tx only /Rx only Transceiver modes.

Tx only, Rx only, and Tx and Rx (Independent) modes are supported only in PMA mode. In 8b10b mode, both Tx and Rx must use the same fabric interface width. Tx/Rx Independent option PCS mode applies for both Tx and Rx and cannot be different within the lane. For example, the Tx cannot be 8b10b when the Rx is 64b66b.

The TXPLL supports Fractional-N frequency synthesizer, and the CDR PLL only supports integer-based synthesis. Typically, the same REFCLK is used for both the TXPLL and CDR PLL for full-duplex lane. The user has the option to use integer-based for the TXPLL if the frequency is achieved without issue.

If the TXPLL uses Frac-N rather than integer-based to synthesize the bit clock, the CDR PLL will not have the Frac-N capability. Consequently, the user needs to determine if the PPM tolerance of the CDR is enough to compensate for the TXPLL rate.