2.3.3 EN/PWRHLD Typical Use Cases
Depending on the presence of a Back-Up supply, two different scenarios can be defined for the turn-on of the MCP16503, as described in the following table.
| Applications With a Backup Bupply | Applications Without a Backup Supply |
|---|---|
 The application starts when VIN ramps up above the UVLO threshold as the EN pin is pulled up to VIN. Note that PWRHLD (= SHDN from MPU) was set to 1 at the time the battery was mounted on the PCB, i.e. at the time of manufacturing. The power channels of MCP16503 are turned off by the MPU by setting SHDN = 0. The MPU is then in backup mode. If supported, the DDR can also be placed in backup self-refresh mode (BSR) by setting LPM = 1 before SHDN = 0. To wake up the application from backup mode, a wake-up event must be generated for the SHDWC (Shutdown and Wake-Up Controller) of the MPU. This can be an internal event (e.g. RTC, RTT alarm, TAMPER detection) or an event on a I/O of the SHDWC (e.g. wake-up from a wireless module). The MPU will then set SHDN = 1 and the low-to-high transition of PWRHLD will cause the MCP16503 to restart. If VIN is cycled while the MPU is in backup mode (SHDN=0), the MCP16503 restarts automatically and sends a wake-up event to the MPU on nSTRTO (WKUP). If this wake-up event was not enabled in the MPU SHDWC configuration, SHDN will stay low and the MCP16503 will turn off at the end of the start-up sequence, because PWRHLD has not been set high. If this wake-up event was enabled, SHDN will immediately go high thus confirming the start-up sequence for the MCP16503, and the application will restart. |  The application starts when VIN ramps up above the UVLO threshold as the EN pin is pulled up to VIN. PWRHLD (= SHDN from MPU) is set to 1 as soon as VBAT (= VDDIO) is above its internal POR threshold (around 1.5V). The power channels of MCP16503 are turned off by the MPU by setting SHDN = 0. In this case, the MPU is NOT in backup mode, it is simply completely OFF. Hibernate mode cannot be used because PWRHLD cannot be set to 0. Doing so would cause the PMIC to shut down and it would not restart, as the battery is not present. Without the battery, the VBAT voltage drops to 0 V immediately after the PMIC shuts down. From the OFF state, the application can only be restarted by cycling power on VIN. |
PWRHLD, LPM and HPM define different power states which are illustrated in the following Table 2-1. These are default definitions for the targeted typical application scenario of an MPU when powering DDR memories and therefore may be different for other application configurations.
The logic value of HPM input pin is masked (seen by the internal logic as “0”) until a specific I2C command is issued (HPMPEN bit must be set to “1”) only after PSEQ_DONE bit is set and start-up sequence is completed. The reason is the HPM is a generic GPIO, whose status at the MPU power-up time could be undefined. The HPMPEN bit is reset only through power cycling or an EN pin high to low transition in OFF mode.
After the software has issued the unmask HPM command through I2C, it is safe to assume that the HPM status is well defined and the HPM signal can be used to enter/exit High-Performance Mode. All the following power states assume that EN is already HIGH.
| PWRHLD | LPM | HPM | Buck1 | Buck2 | Buck3 | Buck4 | LDO1 | LDO2 | nRSTO | Power State |
|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | OFF | OFF | OFF | OFF | OFF | OFF | LOW | OFF |
| 0 | 1 | 0 | OFF | ON Auto PFM | OFF | OFF | OFF | OFF | LOW | HIBERNATE |
| 1 | 1 | 0 | ON Auto PFM | ON Auto PFM | ON Auto PFM | ON Auto PFM | ON | ON | High-Z | Low-Power Mode |
| 1 | 0 | 0 | ON FPWM | ON FPWM | ON FPWM | ON FPWM | ON | ON | High-Z | Active |
| 1 | 0 | 1 | ON FPWM | ON FPWM | ON FPWM | ON FPWM | ON | ON | High-Z | High-Performance Mode |
Other logic combinations of PWRHLD, LPM and HPM (after HPM unmasking) are forbidden.
The initial state is the OFF state (shutdown).
The process by which the MCP16503 abandons the OFF state and enters the other possible power states is defined as the Power-Up Sequence, which is described in the relevant section Typical Power-Up Sequence and Timing.
The following state diagram shown in Figure 2-1 illustrates the power states of MCP16503 and their typical and/or permissible dynamic transitions. Special care must be taken when performing power mode transitions, as the PMIC supports different output voltage levels in each mode. During a transition from OFF to Low-Power mode, the device necessarily passes through Active mode, causing the output voltage to first rise to the voltage configured for Active mode. The device then transitions to Low-Power mode, during which the output voltage changes again to the voltage configured for Low-Power mode. If the voltage settings for Active and Low-Power modes differ, this results in multiple output voltage changes during the transition, which must be carefully considered during system design.