2.4.1 Typical Power-Up Sequence and Timing

The start-up sequence can be initiated in two different ways, also depending on the presence of a back-up supply in the application:

  1. EN event (EN pin pulled HIGH) with PSEQ_DONE bit cleared, maintained by PWRHLD assertion

    In applications with backup battery, the PWRHLD signal is typically already high before the EN event.

  2. A low-to-high transition of the PWRHLD signal with PSEQ_DONE bit set, regardless of the EN event. This is only possible in applications with backup supply. This mode is typically originated by an external wake-up event asserted by a peripheral device to the MPU Shutdown and Wakeup Controller (SHDWC), which is still powered in backup mode.

Note that the event 1 and 2 needs the assertion of PWRHLD to have the power-up sequence completed successfully. If PWRHLD is not yet HIGH at the time nRSTO is supposed to be asserted, the PMIC automatically initiates a turn-off sequence, without any positive glitches on nRSTO.

Delay t1 acts as a de-bouncing delay of the EN event. Therefore, EN must be detected HIGH continuously during t1 to validate the start-up event and initiate the first sequence step. EN pin shall stay high, otherwise it can trigger a power down sequence when timing condition is fulfilled. Please refer to the next section for the details.

The following timing diagrams show the typical sequence for the first case:

Figure 2-3. EN Power Start-up Scenario: EN Short to VIN
Figure 2-4. EN Power Start Scenario: EN Delayed

Where:

  • t1 = delay from EN rising to first output, VOUT1 starting (SEQ[1:0] = 00, default DELAY[2:0]  =  001 i.e. 0.5 ms + device wake-up time)
  • t2 = time from VOUT1 established to VOUT2 starting (SEQ[1:0] = 01, default DELAY[2:0] = 101 i.e. 8 ms)
  • t3 = time from VOUT2 established to VOUT3, VOUT4 starting (SEQ[1:0] = 10, default DELAY[2:0] = 100 i.e. 4 ms)
  • t4 = time from VOUT3 established to nRSTO de-assertion (default RSTDLY[2:0] = 100 i.e. 16 ms)
  • t5 = setup/hold times, min. 0 ms (internal filtering applies)
  • “established” means the relevant power channel POK bit has gone HIGH
  • t1 to t3 are programmable through DELAY[2:0] bits, t4 is programmable through RSTDLY[2:0] bits

For power supplies starting at t1, the DELAY[2:0] value is the additional delay time interval added to the minimum achievable wake-up time.

The following timing diagram of Figure 2-5 shows the typical sequence for the second case:

Figure 2-5. Start-Up From PWRHLD Timing Diagram

Where:

  • t1 = delay from PWRHLD asserted to first output VOUT1 starting (SEQ[1:0] = 00, default DELAY[2:0] = 001 i.e. 0.5 ms + device wake-up time)
  • t2 = time from VOUT1 established to VOUT2 starting (SEQ[1:0] = 01, default DELAY[2:0] = 101 i.e. 8 ms)
  • t3 = time from VOUT2 established to VOUT3, VOUT4 starting (SEQ[1:0] = 10, default DELAY[2:0] = 100 i.e. 4 ms)
  • t4 = time from VOUT3 established to nRSTO de-assertion (default RSTDLY[2:0] = 100 i.e. 16 ms)
  • “established” means the power channel POK bit has gone HIGH

For all the sequences described above, LPM can be assumed to be LOW. The MPU will assert LPM after some time, based on software decision, to enter the Low-Power modes.