5.3 HPM Pin / HPMPEN Bit

The HPM pin is meant to be driven by a GPIO of the host MPU for the purpose of entering a software-defined high-performance mode. Its usage is optional, and it should be connected to ground if it is not used.

For example: SAMA7G MPUs will typically use the HPM pin to switch the VDDCPU rail voltage (supplied by a buck channel) to a higher voltage such that higher clock frequencies can be supported (DVS operation, see section Dynamic Voltage Scaling (DVS) Operation). The required overdrive voltage level in HPM mode needs to be defined by I²C prior to entering DVS operation. If no action is taken, the HPM voltage value will default to the ACTIVE mode default value.

The HPM pin needs to be enabled (unmasked) through I²C by setting bit HPMPEN in register SYS-CFG. If HPMPEN bit is not set, the internal logic will be insensitive to the HPM pin level, which will always appear internally as a logic “0”.

The HPMPEN bit is not automatically cleared due to a start-up or to a restart sequence after a fault. Also, the DVS voltage level definition stored in the HPM registers is not reset to the Active mode one.

Therefore, if for any reason the HPM pin remains high (or returns to high logic level) during the start-up/restart sequence while the HPMPEN bit has been previously set, the MCP16503 will move to the high-performance mode immediately after the start-up/restart sequence has successfully terminated. Thus, if the DVS voltage level defined in HPM mode is different than the voltage level defined in Active mode, the channel under consideration will immediately move to the HPM mode voltage level as soon as nRSTO is de-asserted.

While the DVS voltage level is not typically dangerous for the VDDCPU rail generated by a buck channel, if the behavior described above is not desirable, the following countermeasures can be considered:

- connect the HPM pin to a GPIO which is low by default at start-up;

- clear by software the relevant GPIO at the beginning of the software execution / configuration routine and/or clear the HPMPEN bit by I²C command.

Also note that the channel (typically Buck1, VDDIO) powering the MPU voltage domain to which the GPIO driving the HPM pin belongs, should be always defined ON in HPM mode.

Failing to do so would set the HPM pin low again shortly after it has been set high, thereby generating a cyclic behavior where the relevant channel turns ON and OFF indefinitely.

If the LPM pin goes high (with PWRHLD = high) while HPM is low, the MCP16503 will move to Low-Power state. If HPM goes high after that, the MCP16503 will ignore it and it will stay in Low-Power state, as long as LPM = high.

On the other hand, if HPM goes high first (thus PWRHLD = HPM = 1, LPM = 0), the device remains in HPM state even if LPM is asserted high. To go to Low-Power State, HPM must be de-asserted first.