5.2 Dynamic Voltage Scaling (DVS) Operation

Dynamic Voltage Scaling is not a special mode of operation. When the state machine moves from one state to another, and the content of the regulator voltage in the new state is different from the previous one (assuming the regulator is ON in both the initial and final state), the output voltage of the regulator will be automatically updated in 25 mV (or 50 mV for Buck1 and LDOs) increments/decrements to reach the value which is defined for the final state.

This also happens if the regulator voltage is updated through I²C, without any power mode state change.

The step rate is programmable, and it is derived from the switching frequency clock. The values are as described in section Dynamic Voltage Scaling Rate Programming Bits (t_ramp).

Internal filtering time constants for the reference DAC steps and the finite response time of the control loop help in smoothing out the resulting ramp shape visible at the output of the regulator(s).

During DVS transitions:

• The Buck converters will operate in FPWM, to allow a predictable transition time in both the rising and falling DVS transitions.
• LDO: when the transition happens in the negative direction (i.e. decreasing voltage), the Active Discharge load will be activated during the transition, in order to speed up the transition time. This is to facilitate the support of dual-voltage SD Cards

The POK will not be de-asserted during rising DVS transitions because of change in reference (DAC) voltage.

During DVS transition, changes in POK logic value are inhibited until the transition is completed.