5.6 Maximum Simultaneous Capacitive and DC Loading in Soft-Start and DVS
The Current-Mode architecture of the Buck channels in the MCP16503 make them tolerant to additional capacitive loads, from the stability point-of-view.
However, since the hiccup mode overcurrent protection is also enabled during Soft-Start and DVS ramping, the user needs to be aware that additional load capacitance distributed on the application board may cause the intervention of the hiccup mode protections under dynamic conditions (rising output voltage).
This is especially important for Buck1, since the I/O rail (typically 3.3V) can be used for a wide variety of loads and its total distributed capacitive load could significantly exceed the minimum recommended nominal capacitance value (i.e. 22 μF).
Using the symbols listed in the DC/AC Characteristics table, the following equation establishes the maximum allowable capacitive load Cadd_max to prevent the cycle-by-cycle current limit from being engaged.
Complying with this condition will guarantee that hiccup mode overcurrent protection will not be activated during the Soft-Start ramp or DVS transitions in the positive direction.
Where:
- ILIM_HS: High-Side MOSFET Current Limit
- r : ratio of the peak inductor current ILpk to average inductor current at the point where ILpk = ILIM_HS. For simplicity, assume r = 1 since the peak-to-peak inductor current ripple will be small in comparison to the average inductor current value when the high-side current limit is engaged.
- IOUT: Output current of the Buck converter
- Vstep: Output voltage step in SS (or DVS)
- SSR_XX: Soft-Start Rate (or DVS Rate), XX = 00, 01, 10, 11
- fsw: switching frequency
- COUT: output capacitance already present on the Buck converter output (typically COUT = 22 μF)
Failing to comply with the conditions formulated above does not necessarily mean that hiccup mode protection will be engaged. The digital filtering provided in the hiccup mode overcurrent algorithm, as described in section Overcurrent Protection (Buck Channels), provides immunity to single and even multiple cycle-by-cycle current limit events, and allows operation in proximity of the high-side current limit for significant amount of time during the Soft-Start or DVS ramping.
As a consequence, the maximum value of additional capacitance Cadd_max that can be observed by experiments is significantly higher than the limit calculated with the formula.
