16.1.2 16.2.2 Sequential Logic

16.1.2.1 DFN1

D-Type Flip-Flop.

Table 16-57. DFN1 I/O
Input	Output
D, CLK	Q

Table 16-58. DFN1 Truth Table
CLK	D	Q_n+1
not Rising	X	Q_n
—	D	D

16.1.2.2 DFN1C0

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D-Type Flip-Flop with active-low Clear.

Table 16-59. DFN1C0 I/O
Input	Output
D, CLK, CLR	Q

Table 16-60. DFN1C0 Truth Table
CLR	CLK	D	Q_n+1
0	X	X	0
1	not Rising	X	Q_n
1	—	D	D

16.1.2.3 DFN1E1

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D-Type Flip-Flop with active high Enable.

Figure 16-30. DFN1E1

Table 16-61. DFN1E1 I/O
Input	Output
D, E, CLK	Q

Table 16-62. DFN1E1 Truth Table
E	CLK	D	Q_n+1
0	X	X	Q_n
1	not Rising	X	Q_n
1	—	D	D

16.1.2.4 DFN1E1C0

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D-Type Flip-Flop, with active-high Enable and active-low Clear.

Table 16-63. DFN1E1C0 I/O
Input	Output
CLR, D, E, CLK	Q

Table 16-64. DFN1E1C0 Truth Table
CLR	E	CLK	D	Q_n+1
0	X	X	X	0
1	0	X	X	Q_n
1	1	not Rising	X	Q_n
1	1	—	D	D

16.1.2.5 DFN1E1P0

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D-Type Flip-Flop with active-high Enable and active-low Preset.

Table 16-65. DFN1E1P0 I/O
Input	Output
D, E, PRE, CLK	Q

Table 16-66. DFN1E1P0 Truth Table
PRE	E	CLK	D	Q_n+1
0	X	X	X	1
1	0	X	X	Q_n
1	1	not Rising	X	Q_n
1	1	—	D	D

16.1.2.6 DLN1

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Data Latch.

Figure 16-33. DLN1

Table 16-67. DLN1 I/O
Input	Output
D, G	Q

Table 16-68. DLN1 Truth Table
G	D	Q
0	X	Q
1	D	D

16.1.2.7 DLN1C0

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Data Latch with active-low Clear.

Table 16-69. I/O
Input	Output
CLR, D, G	Q

Table 16-70. Truth Table
CLR	G	D	Q
0	X	X	0
1	0	X	Q
1	1	D	D

16.1.2.8 DLN1P0

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Data Latch with active-low Preset.

Table 16-71. DLN1C0 I/O
Input	Output
D, G, PRE	Q

Table 16-72. DLN1C0 Truth Table
PRE	G	D	Q
0	X	X	1
1	0	X	Q
1	1	D	D

16.1.2.9 SLE

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Sequential Logic Element.

Table 16-73. SLE I/O
Input		Output
Name	Function	Q
D	Data input
CLK	Clock input
EN	Active-High CLK enable
ALn	Asynchronous Load. This active-Low signal either sets the register or clears the register depending on the value of ADn.
ADn¹	Static asynchronous load data. When ALn is active, Q goes to the complement of ADn.
SLn	Synchronous load. This active-Low signal either sets the register or clears the register depending on the value of SD, at the rising edge of clock.
SD¹	Static synchronous load data. When SLn is active (that is, low), Q goes to the value of SD at the rising edge of CLK.
LAT¹	Active-High Latch Enable. This signal enables latch mode when high and register mode when low.

ADn, SD, and LAT are static signals defined at design time and need to be tied to 0 or 1.

Table 16-74. SLE Truth Table
ALn	ADn	LAT	CLK	EN	SLn	SD	D	Q_n+1
0	ADn	X	X	X	X	X	X	!ADn
1	X	0	Not rising	X	X	X	X	Qn
1	X	0	—	0	X	X	X	Qn
1	X	0	—	1	0	SD	X	SD
1	X	0	—	1	1	X	D	D
1	X	1	0	X	X	X	X	Qn
1	X	1	1	0	X	X	X	Qn
1	X	1	1	1	0	SD	X	SD
1	X	1	1	1	1	X	D	D

16.1.2.10 SLE_DEBUG

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The SLE_DEBUG Macro is used to communicate with SmartDebug. The SLE_DEBUG mechanism gives ability to run synthesis while preserving a set of registers. It provides the ability to identify, rename, and classify registers for SmartDebug.