16.1.8 RAM64x12

The RAM64x12 block contains 768 memory bits and is a two-port memory providing one write port and one read port. Write operations to the RAM64x12 memory are synchronous. Read operations can be asynchronous or synchronous for setting up the address and reading out the data. Enabling synchronous operation at the read-address port improves setup timing for the read-address and its enable signals. Enabling synchronous operation at the read-data port improves clock-to-out delay. Each data port on the RAM64x12 memory is configured to a fixed configuration of 64x12.

Functionality

The main features of the RAM64x12 memory block are as follows:

  • There is one read-data port and one write-data port.
  • Both read-data and write-data ports are configured to 64x12.
  • The write operation is always synchronous. The write-address, write-data and write-enable inputs are registered.
  • Setting up the read-address can be synchronous or asynchronous. The read-address registers have an independent enable, synchronous-load and asynchronous-load for synchronous mode operation, which can be bypassed for asynchronous mode operation.
  • The read-data pipeline registers have an independent enable, synchronous-load and asynchronous-load for pipeline mode operation, which can be bypassed for asynchronous mode operation.
  • Therefore, there are four read operation modes:
    • Synchronous read-address without read-data pipeline registers (sync-async)
    • Synchronous read-address with read-data pipeline registers (sync-sync)
    • Asynchronous read-address with read-data pipeline registers (async-sync)
    • Asynchronous read-address without read-data pipeline registers (async-async)
  • There is an independent clock for each port. The memory will be triggered at the rising edge of the clock.
  • Read and write on the same location at the same time results in unknown data to be read.

There is no collision prevention or detection. However, correct data is expected to be written into the memory.

Figure 16-68. Simplified Block Diagram of RAM64x12

Port List

The following table gives the port descriptions.

Table 16-139. Port List for RAM1K20
Pin NamePin DirectionTypeDescriptionPolarity
W_ENInputDynamicWrite port enableHigh
W_CLKInputDynamicWrite clock. All write-address, write-data and write-enable inputs must be set up before the rising edge of the clock. The write operation begins with the rising edge.Rising
W_ADDR[5:0]InputDynamicWrite address—
W_DATA[11:0]InputDynamicWrite-data—
BLK_ENInputDynamicRead port block select. When High, read operation is performed. When Low, read-data will be forced to zero. BLK_EN signal is registered through R_CLK when R_ADDR_BYPASS is Low.High
R_CLKInputDynamicRead registers clock. All read-address, block- port select and read-enable inputs must be set up before the rising edge of the clock. The read operation begins with the rising edge.Rising
R_ADDR[5:0]InputDynamicRead-address—
R_ADDR_BYPASSInputStaticRead-address and BLK_EN register select.Low
R_ADDR_ENInputDynamicRead-address register enable.High
R_ADDR_SL_NInputDynamicRead-address register synchronous load.Low
R_ADDR_SDInputStaticRead-address register synchronous load data.High
R_ADDR_AL_NInputDynamicRead-address register asynchronous load.Low
R_ADDR_AD_NInputStaticRead-address register asynchronous load data.Low
R_DATA[11:0]OutputDynamicRead-data—
R_DATA_BYPASSInputStaticRead-data pipeline register select.Low
R_DATA_ENInputDynamicRead-data pipeline register enable.High
R_DATA_SL_NInputDynamicRead-data pipeline register synchronous load.Low
R_DATA_SDInputStaticRead-data pipeline register synchronous load data.High
R_DATA_AL_NInputDynamicRead-data pipeline register asynchronous load.Low
R_DATA_AD_NInputDynamicRead-data pipeline register asynchronous load data.Low
BUSY_FBInputStaticLock access to FCB.High
ACCESS_BUSYOutputDynamicBusy signal from FCB.High
Tip: Static inputs are defined at design time and need to be tied to 0 or 1.

Read-address and Read-data Pipeline Register Control Signals

The following table describes the functionality of the control signals on the R_ADDR and R_DATA registers.

Table 16-140. Truth Table for R_ADDR and R_DATA Registers
_AL_N_AD_N_BYPASS_CLK_EN_SL_N_SDDQn+1
0ADnXXXXXX!ADn
1X0Not risingXXXXQn
1X0?0XXXQn
1X0?10SDXSD
1X0?11XDD
1X1XXXXDD