2.4.4 ICSP Sequential Read (CMDSEQRD)

This Sequential Read Sequence shifts out the 32-bit VISI register content onto the PGEDx pin, identically to CMDRD, but will internally also execute the following instruction:

MOV.L [W0++], [W8]

The existing VISI content is buffered before execution of this MOV.L instruction, so all 32 bits of VISI appear on PGEDx as they existed before this instruction is executed. However, this instruction is typically used to reload VISI with more data from SFRs, RAM or program space, and it completes execution by the time all bits have shifted out. Therefore, CMDSEQRD is optimized for use in a loop to transfer multiple sequential memory contents out of the target and into the programmer.

As the generated MOV.L instruction references W0 and W8, this command must be preceded with CMDEXEC commands to load W8 with the address of the VISI register and W0 with the read address on the target:

MOV.SL #VISI, W8

MOV.SL #ReadAddress<23:0>, W0

The Sequential Read Sequence is:
  1. The programmer shifts the ‘11’ bits into the device.
  2. One Idle PGECx clock is generated by the programmer to accommodate switching the PGEDx pin direction; the programmer should tri-state PGEDx before the falling edge of this clock as the target device will begin driving bit 0 of VISI at this time.
  3. The programmer shifts in the 32-bit VISI register content from the device. The Least Significant bit of the VISI register is presented first. The device updates each data bit on the falling edge of the PGECx pulse. To accommodate propagation delay of the clock into the device and output delay returning the next bit, the programmer should sample the data from the device on or after the PGECx rising edge.
  4. One Idle PGECx clock is generated by the programmer to accommodate switching the PGEDx pin direction back to an input; the device tri-states PGEDx on the falling edge that completes the VISI bit 31 transfer, so the programmer can begin driving PGEDx anytime during or at the end of this clock.

Unlike CMDEXEC and CMDSEQWR, the CPU will finish execution of the internally generated MOV.L [W0++], [W8] instruction before the final (buffered) bit 31 of VISI is shifted out. This permits back-to-back reissuing of CMDSEQRD to return the next 32 bits of memory without extra clocking following the VISI write.

Figure 2-16 shows an example of CMDSEQRD, where the 0x12345678 data are received by a programmer from VISI.

Figure 2-16. Example of CMDSEQRD Where the Data are Received by a Programmer from VISI