2.4.1 ICSP Instruction Execution (CMDEXEC)

The Instruction Execution Sequence (CMDEXEC) shifts one 32-bit instruction, two 16-bit instructions or half of a 64-bit instruction into the target CPU.

The Instruction Execution Sequence is:

1. The programmer shifts the ‘00’ bits into the device.
2. Then, the programmer sends 32 bits of instruction opcode data to the device. Each PGEDx bit is latched by the device on the rising edge of the PGECx pulse. The CPU executes the instruction(s) over the next 5-10 PGECx clocks while sending the next ICSP command.

When providing 16-bit instruction(s), the first 16-bit instruction to execute must be aligned to the Least Significant 16 bits and followed by another 16-bit instruction in the upper half of the 32-bit data transfer. If only one 16-bit instruction is available, it must be aligned in the low 16 bits and zero-extended out to 32 bits (upper 16 bits encodes a NEOP).

When executing a 64-bit instruction, the first CMDEXEC Sequence will load the 1st instruction word (bits 0-31 of the opcode). A second CMDEXEC Sequence must be issued to load the 2nd instruction word (bits 32-63 of the opcode) and allow the CPU to begin executing the instruction. For 64-bit instructions, the 2nd CMDEXEC Sequence must be sent after the 1st CMDEXEC Sequence without any other intervening ICSP commands; otherwise, the CPU’s instruction flow will be corrupted and an Illegal Opcode Reset may be generated.

Figure 2-13 shows an example where the “MOV.SL #VISI, W8” instruction (load the VISI register address into the W8 register), with opcode 0xA0001F03, is shifted into the CPU.