2.4.3 ICSP Sequential Write (CMDSEQWR)

The ICSP Sequential Write Sequence (CMDSEQWR) permits rapid writes of 32-bit data via an indirect pointer access to RAM or device registers. When the sequence is completed, a 64-bit MOV.L instruction is internally generated, encoding all 32 bits of shifted data and passed to the CPU for execution. The outcome is equivalent to issuing two CMDEXEC Sequences necessary to execute a 64-bit instruction of:

MOV.L #PGEDx<31:0>, [W0++]

This instruction writes the 32 bits of provided data to the memory pointed to by the 4-byte aligned address in the W0 register, then increments the W0 pointer by four. By pre-initializing W0 to a RAM or register address, incrementing locations may be written to, with minimal overhead, simply by executing a series of back-to-back CMDSEQWR sequences. Generally, CMDSEQWR should be used for all data writes of four or more bytes from the programmer to 4-byte aligned sequential addresses.

The Sequential Write Sequence is:
  1. The programmer shifts the ‘10’ bits into the device. As all data follow Least Significant bit first ordering, the ‘0’ bit must be presented on the PGEDx wire before the ‘1’ bit.
  2. Then the programmer sends 32 bits of RAM or SFR data to the device. Each PGEDx bit is latched by the device on the rising edge of the PGECx pulse. The CPU executes the generated MOV.L instruction over the next 5-10 PGECx clocks while sending the next ICSP command.

Figure 2-15 shows an example of the CMDSEQWR Sequence, where 0x12345678 from the programmer is written to the address in the W0 register.

Figure 2-15. CMDSEQWR Sequence Where Data from Programmer are Written to Address in W0 Register