51.10 I/O Graphs

Figure 51-58. Fall Time (SLRxn = b'1) vs. VDD
Figure 51-59. Fall Time (SLRxn = b'0) vs. VDD
Figure 51-60. Rise Time (SLRxn = b'1) vs. VDD
Figure 51-61. Rise Time (SLRxn = b'0) vs. VDD
Figure 51-62. Input Pin with Schmitt Trigger - Maximum VIL vs. VDD
Figure 51-63. Input Pin with Schmitt Trigger - Minimum VIH vs. VDD
Figure 51-64. Input Pin with Schmitt Trigger - Hysteresis vs. VDD
Figure 51-65. Input Pin with LVBUF - Maximum VIL vs. VDD
Figure 51-66. Input Pin with LVBUF - Minimum VIH vs. VDD
Figure 51-67. Input Pin with I2C Trigger - Maximum VIL vs. VDD
Figure 51-68. Input Pin with I2C Trigger - Maximum VIH vs. VDD
Figure 51-69. Input Pin with SMBus - Maximum VIL vs. VDD
Figure 51-70. Input Pin with SMBus - Maximum VIH vs. VDD
Figure 51-71. Reset Pin VIL vs. VDD
Figure 51-72. Reset Pin VIH vs. VDD
Figure 51-73. Output Pin - Maximum VOL vs. Current, VDD = 1.8V
Figure 51-74. Output Pin - Minimum VOH vs. Current, VDD = 1.8V
Figure 51-75. Output Pin - Maximum VOL vs. Current, VDD = 3.0V
Figure 51-76. Output Pin - Minimum VOH vs. Current, VDD = 3.0V
Figure 51-77. Output Pin - Maximum VOL vs. Current, VDD = 5.5V
Figure 51-78. Output Pin - Minimum VOH vs. Current, VDD = 5.5V