Figure 51-114. Falling Edge
Response Time vs. VDD (VCM =
VDD/2, SP[1:0] = 0x0)
Figure 51-115. Falling Edge
Response Time vs. VDD (VCM =
VDD/2, SP[1:0] = 0x1)
Figure 51-116. Falling Edge
Response Time vs. VDD (VCM =
VDD/2, SP[1:0] = 0x2)
Figure 51-117. Falling Edge
Response Time vs. VDD (VCM =
VDD/2, SP[1:0] = 0x3)
Figure 51-118. Rising Edge
Response Time vs. VDD (VCM =
VDD/2, SP[1:0] = 0x0)
Figure 51-119. Rising Edge
Response Time vs. VDD (VCM =
VDD/2, SP[1:0] = 0x1)
Figure 51-120. Rising Edge
Response Time vs. VDD (VCM =
VDD/2, SP[1:0] = 0x2)
Figure 51-121. Rising Edge
Response Time vs. VDD (VCM =
VDD/2, SP[1:0] = 0x3)
Figure 51-122. Input Offset
vs. Common Mode Voltage (VDD = 2.0V)
Figure 51-123. Input
Hysteresis vs. Common Mode Voltage (VDD =
2.0V)
Figure 51-124. Input Offset
vs. Common Mode Voltage (VDD = 3.0V)
Figure 51-125. Input
Hysteresis vs. Common Mode Voltage (VDD =
3.0V)
Figure 51-126. Input Offset
vs. Common Mode Voltage (VDD = 5.5V)
Figure 51-127. Input
Hysteresis vs. Common Mode Voltage (VDD =
5.5V)
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