31.5.1 Control A
| Name: | CTRLA |
| Offset: | 0x00 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RUNSTBY | RESSEL | FREERUN | ENABLE | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 7 – RUNSTBY Run in Standby
This bit determines whether the ADC needs to run when the chip is in Standby Sleep mode.
Bit 2 – RESSEL Resolution Selection
This bit selects the ADC resolution.
| Value | Description |
|---|---|
| 0 | Full 10-bit resolution. The 10-bit ADC results are accumulated or stored in the ADC Result register (ADC.RES). |
| 1 | 8-bit resolution. The conversion results are truncated to eight bits (MSBs) before they are accumulated or stored in the ADC Result register (ADC.RES). The two Least Significant bits are discarded. |
Bit 1 – FREERUN Free-Running
Writing a '1' to this bit will enable the Free-Running mode for the data acquisition. The first conversion is started by writing the STCONV bit in ADC.COMMAND high. In the Free-Running mode, a new conversion cycle is started immediately after or as soon as the previous conversion cycle has completed. This is signaled by the RESRDY flag in ADCn.INTFLAGS.
Bit 0 – ENABLE ADC Enable
| Value | Description |
|---|---|
| 0 | ADC is disabled |
| 1 | ADC is enabled |